Transition Elements as Deep Level Dopant

Transition Elements as Deep Level DopantHIGH RESISTIVITY SILICON DEEP-LEVEL DOPING COMPENSATION USING primary GOLDINTRODUCTION1.1Research BackgroundMo zero(prenominal)eithic atomize integrated circuit (MMIC) is a microwave circuit in which some(prenominal) active and nonoperational components be fabricated on the same semiconductor substratum 1. The development of MMICs has been augmented by the blue demand for extravagantly-speed cunnings operating at microwave frequency ranging between 300 MHz and 300 GHz. Their advantages of being small, light, and cheap in large quantities have allowed the proliferation of highschool frequency devices such as cellular phones. However, a problem exit arise when standard silicon (Si) substratum is employ to operate in super high frequency environment (SHF). The high absorption of microwave power will be caused by the solid ground free carriers present in the substrate 2. Therefore, low loss and high opposition substrates are needed to eliminate the problem. It can be achieved by reducing the number of background free carriers in the substrate which result in humiliation of circuit performance.The III-V semiconductor materials such as GaAs, GaN and InP has been widely used in the production of high resistance substrates due to their wide wadgap nature. However, the wafer diameter shitd victimisation III-V materials is typically from 4 to 6 3. This add-ons the cost of production since the standard wafer diameter for modern CMOS technology is 12 4. Furthermore, the lattice-mismatch problems will complicate the assembly process, causing the cost to emergence. Therefore, Si has been considered to be an alternative material for the III-V semiconductor compound due to less(prenominal) fabrication complexity and cost. However, the background impurities such as boron will levy the silicon during monocrystalline Si growth causing the increase in substrate losses at microwave take off 5.There have been efforts to use the silicon-on-insulator (SOI) technologies and silicon-on-any thinlyg (SOA) to dominate the problem. The SOI wafers can be produced by several regularity actings silicon-on-sapphire (SOS), separation by implanted oxygen (SIMOX), bond and etch-back SOI (BESOI), modishness Cut 6, and epitaxial class transfer (ELTRAN) 7. For SOS approach, a thin film of Si is epitaxially grown on sapphire substrate as shown in jut 1.1. Meanwhile, the other four approaches use a similar impair section of SOI wafer as shown in figure 1.2(b) which consists of trinity layers SOI layer (top layer), buried oxide (BOX) layer (middle layer) and silicon substrate (bottom layer). The purpose of the BOX layer is to electrically set apart a fine layer of SOI layer (where the circuits are placed) from the rest of the Si wafer. The SIMOX approach uses implanted silicon dioxide, SiO2 layer as the BOX layer to decompose the top thin Si layer from Si substrate. condition 1.1 Cross-section of silicon-on-sa pphire (SOS) wafer 8Figure 1.2 A schematic representation of bond and etch-back (BESOI) process 9Apart from the mentioned approaches, BESOI, saucy Cut, and ELTRAN methods involve the wafer bonding proficiency. For BESOI method, the thermally oxidised Si wafer (also known as handle wafer) is bonded to another Si wafer which acts as bond wafer as shown in figure 1.2(a). After the wafer bonding process, the top wafer will be etched to obtain the required thickness for SOI layer as shown in figure 1.2(b). On the other hand, implantation of gas ions, most commonly hydrogen is made after the oxidisation process for Smart Cut method as shown in figure 1.3. The implantation process is meant for layer splitting process to achieve required thickness of SOI layer after the wafer bonding process. The processes involved in ELTRAN method is shown in figure 1.4. The ELTRAN method uses similar procedures in Smart Cut with the difference in use of double layer porous Si layer instead of implantatio n of hydrogen ions. The advantage of using Smart Cut and ELTRAN methods is that the initial wafer or seed wafer can be reused for the same process.Figure 1.3 Smart Cut process for production of SOI wafers 9Figure 1.4 ELTRAN process flow based on seed wafer reusage 7Meanwhile, the SOA technology is achieved by gluing a fully-processed SOI substrate to another substrate such as glass and alumina 10. However, the on-chip dissipation which could cause thermal breakdown had been proven to be a severe issue 11. Therefore, there is a need to look for the alternative to SOI and SOA wafers, which is the high electric resistance protrude Si substrate. In 2009, International Technology Roadmap for Semiconductors (ITRS) had stressed the importance of high electric resistance Si in radio frequency (RF) and analog/mixed signal (AMS) CMOS application 12.There are generally cardinal techniques for Si crystal growth Czochralski (CZ) technique and float-zone (FZ) technique 13. A simplified versi on of CZ puller, which is an apparatus used to produce monocrystalline Si ingots for CZ technique is shown in figure 1.5. The high purity polysilicon, known as electronic grade silicon (EGS) is persisted in a rotating silica or quartz crucible. A seed crystal is placed in the melt and then slowly withdrawn from the melt. The molten silicon adhering to the crystal freezes or solidifies into a continuous crystal from the seed. The diameter of the crystal can be maintained by controlling the temperature of the crucible and the rotating speed of the crucible and the rod. However, the CZ process will introduce contamination to the monocrystalline Si due to the presence of oxygen, carbon monoxide and impurities such as boron and phosphorus.Figure 1.5 Czochralski crytal puller. CW represent clockwise rotation and CCW represents counter clockwise rotation 13The FZ process, on the other hand, produces Si crystals with lower contamination as no crucible is used in the process. FZ crystals a re mainly used for high power and high voltages devices due to its high resistor. There is a commercially unattached high resistance FZ-Si technology called HiRes 14. The pot electrical resistance of Si produced through HiRes is up to 70 k-cm, which is suitable for future GHz and THz application. However, it is not suitable for modern CMOS processing since its maximum wafer diameter is limited to 8, which will increase the cost. Therefore, there is a need to produce high resistivity good deal CZ-Si substrate due to its low fabrication cost. Therefore, CZ process is still the most widely used method in the manufacturing of single crystal silicon.In 2003, Mallik et al. 2 introduced a new root word in developing a semi-insulating silicon through a method called mysterious-level doping concentration using 3d transition elements. It showed that there is orifice to produce high resistivity plenty CZ-Si substrate using deep level doping compensation. Following this work, Mallik et al. 5 managed to produce CZ-Si raft substrate using Mn with resistivity of up to 10 k-cm. Jordan et al. has also used Au to produce CZ-Si wafer with bulk resistivity of up to 180 k-cm 15. The use of Au-compensated high resistivity bulk Si substrate has been proven by Nur Z. I. Hashim et al. to be able to suppress the parasitic surface conduction (PSC) effect 16.1.2Problem StatementThe paper introduced by Mallik et al. 2 on developing high resistivity bulk Si substrate through deep-level doping compensation is solely based on p- emblem CZ-Si. Even though high resistivity bulk Si substrate has been proven to be achievable using p-type CZ-Si, it has been shown in the work by Jordan et al. 15 that higher magnitude of Au-compensated high resistivity bulk Si substrate can be achieved by using n-type CZ-Si. The potential and problem of using transition elements other than Au as the deep level dopants to produce high resistivity bulk n-type CZ-Si substrate have not been discussed by the work mentioned above.1.3Objectives of ResearchThere are three main objectives that must be met in this research standTo investigate the potential of using transition elements as deep level dopant for n-type Si substrate as compared to p-type Si substrate.To analyse the result obtained through numerical calculation using MATLAB by comparing it with the experimental data.To make comparative study on the resistivity and effectiveness of the high resistivity bulk substrate produced using n-type CZ-Si with other materials such as III-V semiconductor materials.1.4Scope of ResearchThe scope of this project is to analyse the resistivity plot generated by numerical calculation using MATLAB. The potential and effectiveness of each of the transition elements as deep level dopants for n-type CZ-Si will be discussed in this work. The fabrication and experiment of high resistivity bulk n-type CZ-Si substrate will not be conducted in this work. The experimental data used for comparison with the r esult of numerical calculation is obtained from Dr. Nur Zatil Ismah Hashim which was done at Southampton Nanofabrication Centre in 2015.LITERATURE REVIEW2.1IntroductionThere are several methods to produce high resistivity bulk Si substrate, namely proton implantation method, helium-3 ion tool and deep-level doping compensation method. Both proton implantation method and helium-3 ion pecker use the charge housings to reduce the current conduction by background free carriers. Meanwhile, the deep-level doping compensation method use the deep dopants to compensate the change dopants in the Si substrate.2.2Proton nidation MethodOne of the methods to increase the resistivity of CZ-Si substrate is through proton implantation method. The bombardment of protons into Si bulk structure will create defects which can pickle mobile carriers. Therefore, the carrier lifetime is low due to the presence of defects, which prevents the mobile carriers from conducting current freely in the substrat e. Table 2.1 summarizes the studies conducted to produce high resistivity bulk CZ-Si substrate using proton implantation method.Table 2.1 Studies on high resistivity bulk CZ-Si substrate using proton implantation method.ContributorYearProton Implantation qualification (MeV)Resistivity of the Produced Substrate (-cm)Li19890.18103Liao et al.199830106Wu et al.200010106Rashid et al.200217.4105In 1989, Li 17 managed to produce a high resistivity layer beneath Si surface layer using proton implantation and two-step annealing process. The implantation of proton and annealing process formed the buried defect layer with a resistivity of up to 103 -cm. Meanwhile, Liao et al. created semi-insulating pieces within silicon substrate with a resistivity of 1 M-cm 18. It was achieved by bombarding proton beams at 30 MeV from a compact ion cyclotron to the surface of Si substrate. Following this work, the Si substrate with similar resistivity had been produced by Wu et al. using a lower proton imp lantation dynamism, which is 10 MeV 19. In 2002, Rashid et al. reported a Si substrate with a resistivity of 0.1 M-cm produced through their six-step implantation method using an implantation power of 17.4 MeV 20.The high-Q inductors and high transmission gain integrated advance have been realised on the high resistivity Si substrate by Liao et al. and Rashid et al. respectively 18, 20. However, the high process cost is needed for proton implantation method as an enormous dose of 1015 cm-2 to maintain the resistivity of the originally 15 -cm Si substrate to be higher than 1014 -cm 21.2.3Helium-3 Ion Irradiation TechniqueIn 1987, helium-3 ion dick technique has been used for carrier lifetime control of silicon power devices 22. The charge trappings created by the helium irradiation and Coulomb scattering of the aerated trap will prevent the conduction of current by free mobile carriers in the substrate 23. Therefore, a high resistivity Si bulk substrate can be realised by the red uction in carrier lifetime.In 2014, N. Li et al. reported a high resistivity region created within CZ-Si substrate with a resistivity of everywhere 1.5 k-cm using a dose of 1.51013 cm-2 of helium-3 ions 24. The produced high resistivity Si substrate has been used by N. Li et al. in both work for substrate noise isolation improvement in a CMOS process and quality factor improvement in on-chip spiral inductors 24, 25. R. Wu et al. has also used helium-3 ion irradiation technique in their work on radiation efficiency improvement in 60-GHz on-chip dipole antenna 23.The helium-3 ion irradiation technique has the advantage of saving the product cost up to 97% as compared to proton implantation method by reducing the dose amount from 1.01015 cm-2 to 1.51013 cm-2 24, 25. However, the helium-3 ion irradiation technique is comparably less studied and the problem associated with this technique has not been discussed in the work mentioned above.2.4Deep-Level Doping Compensation MethodThe idea of creating high resistivity bulk CZ-Si substrate using deep-level doping compensation has been proposed by Mallik et al. in 2003 2. The basic principle of this method is compensating shallow impurities with deep impurities, i.e. shallow presenters are being compensated by deep acceptors (as shown in figure 2.1) whereas shallow acceptors are being compensated by deep donors (as shown in figure 2.2).Figure 2.1 Compensation between shallow donors and deep acceptors 26Figure 2.2 Compensation between shallow acceptors and deep donors 26As illustrated in figure 2.1, deep acceptors introduced an energy level at EA, which is close to the unalienable Fermi level. The deep acceptors which are negatively charged attract the minority carrier holes to be pin down at EA level. The electrons from shallow donors are initially phrenetic to the conduction slew, then fall to EA level to recombine with the holes. On the other hand, the positively charged deep donors introduced an energy level at ED as shown in figure 2.2. The minority carrier electrons are attracted and trapped at ED level while the holes from shallow acceptors will fall into valence band. The trapped electrons at ED level then fall into valence band to recombine with the holes. Therefore, there is no generation of free carriers which reduces the resistivity of the substrate in both cases.Figure 2.3 shows the resistivity of Si at 300K with a background boron concentration of 1014 cm-3, compensated using deep donor impurities with generic energy level positions below conduction band edge, ED. It can be observed that the resistivity of Si increases until a maximum value is reached while the concentration of deep donors, ND increases. The resistivity is low initially due to undercompensation caused by insufficient number of deep donors. The maximum value of the resistivity of Si is reached when deep donors simply compensate the boron acceptors. Further increase in ND causes overcompensation which results in a fall in the resistivity of Si, making the substrate tends to become n-type.Figure 2.3 Calculated resistivity of Si at 300K as a function of generic donor concentration for background boron concentration of 1014 cm-3 2Table 2.2 Positions of energy levels of transition elements in Si 27ElementDonor level below EC (eV)Acceptor level above EV (eV)Co0.890.82Pd0.840.9Au0.780.56Ag0.750.545V0.450.92Mn0.421.0Pt0.3140.889It can be noted that the resistivity peaks are sharper for ED which is lower than 0.3 eV while the resistivity the Great Compromiser high over a range of relatively low concentration values for larger values of ED. For small values of ED, almost all donors are ionised and take part in the compensation since the donor energy level is closer to the conduction band than Fermi level. A slight increase in ND causes the resistivity to decrease sharply, changing the material to n-type. Meanwhile, for large values of ED, the donor level is near intrinsic Fermi level and less fract ion of deep donors is ionised. Therefore, the compensation change gradually with the increase in ND and the resistivity remain high over a wide range of ND.The transition elements are used as deep level dopants as they introduce a pair of deep donor and deep acceptor levels into the Si band gap as shown in table 2.2. The deep dopant energy levels introduced by the transition elements pin the Fermi level near the middle of the Si band gap as shown in figure 2.4 15. Thus, high resistivity CZ-Si substrate can be achieved by capturing the free carriers by deep impurities, which reduces the concentration of background free carrier.Figure 2.4 Fermi level pin by deep levels introduced by transition elements 15Figure 2.5 Calculated resistivity of Si at 300K as a function of Au, Ag, Co and Pd for three different background boron concentration in cm-3 2Figure 2.6 Calculated resistivity of Si at 300K as a function of (a) Pt (b) V and (c) Mn concentrations for three different background boron c oncentrations in cm-3 2Figure 2.7 Calculated resistivity of Si as a function of Au concentration for n-type and p-type Si with a shallow doping concentration of 1014 cm-3 28The transition element dopants are generally grouped into two categories Au, Ag, Co and Pd are in first category whereas Pt, V and Mn are in second category. As illustrated in figure 2.5, the resistivity of p-type CZ-Si substrate increases with increasing concentration of the deep dopants in first category. The behaviour of impurities in first category is due to presence of both deep donor and acceptor levels very near intrinsic Fermi level of Si bandgap. For Au and Ag, the resistivity of Si reaches a plateau at the concentration of deep dopants over 1016 cm-3 for three different background boron concentration. The reason for the slight difference in the behaviour of Au and Ag is that the both donor and acceptor level is nearer to the middle in the Si bandgap as compared to Co and Pd.For the second category of de ep dopants, the resistivity of p-type CZ-Si reaches a peak and then reduce sharply with the increase in the concentration of the deep dopants as shown in figure 2.6. The reason of the difference in the behaviour is that the impurities in second category have all donor or acceptor level near the intrinsic Fermi level. Therefore, the dopants in second category can only compensate for a single type of doped silicon substrate.The effect of using 3d transition elements as deep level dopants in n-type CZ-Si substrate has not been shown in the work by Mallik et al. Meanwhile, it is shown in the work by Jordan et al. that higher bulk resistivity of Au-compensated Si substrate can be achieved by using n-type CZ-Si as shown in figure 2.7 28. The n-type Au-compensated Si substrate with resistivity up to 70 k-cm has been used by Nur Z. I. Hashim et al. for realisation of coplanar waveguides (CPW) on the substrate 29. Therefore, the potential and problem of using 3d transition elements for deep level compensation in n-type CZ-Si substrate will be discussed in this work.2.5SummaryThe realisation of high resistivity bulk Si substrate using proton implantation method and helium-3 ion irradiation technique was studied. The fabrication of high-Q inductors and antenna has been done on the Si substrate produced using both methods. However, there are problems associated with both methods such as high product cost for proton implantation method and being comparably less studied for helium-3 ion irradiation. Therefore, the idea of creating a semi-insulating silicon substrate using deep-level doping compensation with 3d transition elements was proposed by Mallik et al. in 2003. The deep-level doping compensation method has since been well studied and used for the fabrication of coplanar waveguides and inductors by Nur Z. I. Hashim et al.References1I. D. Robertson and S. Lucyszyn, RFIC and MMIC Design and Technology. IET, 2001.2K. Mallik, R. J. Falster, and P. R. Wilshaw, Semi-insul ating silicon using deep level impurity doping problems and potential, Semicond. Sci. Technol., vol. 18, no. 6, p. 517, 2003.3Products Capabilities EpiWorks, EpiWorks. Online. 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